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\section{The TGCs for the New Small Wheel}
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%%% ====================================================================


In this section of the Appendix we present more technical details about the sTGC concept.


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\subsection{Latency of the sTGC trigger}
\label{appendix:Latency}
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%%% ====================================================================

To be used in phase I of the LHC upgrade, the overall trigger latency must be below a value of 2.55
$\mu s$. This means for the sTGC trigger that the signals from the chamber frontend have to arrive
at the input of the Sector Logic not later than 1.05~$\mu s$ after the occurence of the collision
at the primary vertex. 

The layout of the trigger and readout electronics for the sTGCs is presented in
Fig.~\ref{appendix:TGC1}. The delays calculated for each step are listed in 
Table~\ref{appendix:latency}.

A demonstrator for this readout concept has been developed and measurements of the respective
latencies will soon be available (\ref{appendix:TGC2}).


%%%%  \item {\it Latency (calculation, measurement with demonstrator)}

%%%%%%%%%%%%%%
\begin{figure}[!htb]
   \centering
%%\vspace{-2 pt}
%%% \includegraphics[width=16cm]{Figures/TGC2.pdf}
\includegraphics[width=14cm]{Figures/TGC2}

\vspace{8mm}

\caption{Schematic layout of trigger and readout as presently implemented in a
demonstrator.}

\label{appendix:TGC1}
\end{figure}
%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%
 \begin{table}[!htb]
    \centering
    \begin{tabular}{lrrl}
      & Min (ns) & Max (ns) & notes  \\
      \hline
TOF from interaction point to SW (10~m)   & 35 & 35 & \\
 Propagation delay in chamber             & 25 & 25 & \\
 ASD                                      & 10 & 10 & \\
On chamber cabling (1.5-2.5~m) to selector&  8 & 13 & 5~ns/m \\
 up- to down-stream package (50~cm)       &  0 &  3 & \\
 delay for pad trigger and deskew         & 15 & 25 & \\
 selector                                 &  5 & 10 & switch \\
serializer                                &  5 & 10 & \\
deserializer                              &  8 & 16 & \\
Run Length Encoder 	                      & 16 & 24 & \\
latency for the last sample of the pulse  & 64 &100 & depends on shaping time \\
find largest signal                       & 7.5& 15 & \\
centroid of a layer                       & 13 & 25 & 8 layers done in parallel \\
centroid chooser                          &  5 & 10 & \\
centroid average                          &  8 & 15 & \\
tracklet calc (LUT)                       &  8 & 10 &  datasheet BRAM access time =2~ns \\
output serializer                         & 50 & 75 & GBT: 3 clocks \\
fiber to Sector logic 90~m                &495 &495 & 5.5~ns/m \\
 \hline
                                          & {\bf 776} & {\bf 916} \\
      \hline
    \end{tabular}
	
	\caption{Latency calculation - The table shows the latency with the insertion of the
precision strip trigger logic into the existing path from the Inner Layer coincidence
logic to the Sector Logic. We take as a model the Xilinx Virtex6. All numbers are
estimates except that for the centroid finder for which a realistic design has been
simulated.}
	\label{appendix:latency}
  \end{table}
%%%%%%%%%%%%%%%%%%%%%%%%

\vspace{2mm}

%%%%%%%%%%%%%%%
\begin{figure}[!htb]
   \centering

%%%   \includegraphics[width=16cm]{Figures/TGC15.pdf}
\includegraphics[width=0.6\linewidth,clip]{Figures/TGC15}
\caption{The trigger demonstrator board based on a commercial evaluation board.}
\label{appendix:TGC2}
\end{figure}
%%%%%%%%%%%%%%%

\newpage

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\subsection{Time schedule for the sTGC project}
\label{appendix:TGC_project}
%%%
%%% ====================================================================

The schedule for prototyping, development and production of the sTGC trigger electronics is given in
Table~\ref{tab:TGC2}.


%%%%%%%%%%%%%%%%
 \begin{table}[!htb]
    \centering
    \begin{tabular}{llll}
      Date & Name\\
      \hline
   August 2011   & Demo-0 & Goal    & Demonstrate total latency, ASD to Sector Logic input,  \\
                 &        &         & of pad local trigger, strip selection and sub-sector calculation  \\
                 &        &         & from centroids in an FPGA. \\
                 &        & Includes& KEK TGC ASDs and Carioca ASDs, 4 layers of 16 strips,  \\ 
                 &        &         & 4 layers of 8 or 14 pads, simple non-pipelined readout,  \\
                 &        &         & based on commercial FPGA eval board \\
                 &        & Excludes& links and fibers, pipelined readout, rad tol technolgy\\
   December 2011 & Demo-1 & Goal    & Add channels to do full 8-layer logic, 64 strips per layer \\
                 &        & Includes& based on purpose built FPGA board\\
   		         &	      & Excludes& pipelined readout, rad tol technology \\
   February 2012 & Demo-1a& Goal    & Run with BNL VMM Front End chip (ASD only) \\
   Early 2012    &        &         & Define on-chamber/off chamber split and choose link hardware. \\
                 &        &         & Design on-chamber boards \\
                 &	      &         &produce rad tol ASICs for on-chamber part \\
                 &        &         & 2nd spin of rad tol ASICs  \\
                 &        &         & design off-chamber boards  \\
                 &        &         & production of on- and off-chamber boards  \\
      \hline
    \end{tabular}
    \caption{sTGC trigger development schedule}
    \label{tab:TGC2}
  \end{table}
%%%%%%%%%%%%%%%%%%%%%%%%

\newpage
